 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 22212hkim 20120202-s00004 no.a1220-1/29 semiconductor components industries, llc, 2013 may, 2013 http://onsemi.com ver.1.03 LC87F1D64A overview the LC87F1D64A is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 62.5ns, integrates on a single chip a number of hardware features such as 64k-byte flash rom (onboard programmable), 4096-byte ram, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8- bit timers), 16-bit timers/counter (may be divided into 8-bit timers/counters or 8-bit pwms), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous sio interface (with automatic block transmit/ receive function), an as ynchronous/synchronous si o interface, a uart interface (full duplex), a full-speed usb interface (function cont roller), 12-channel 12-bit a/ d converter w ith 12-/8-bit resolution selector, two 12-bit pwm channels, a system cl ock frequency divider, an infrared remote control receiver circuit, and a 30-source 10-vector address interrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 3.0 to 5.5v, of voltage source. ? block-erasable in 128 byte units ? writes data in 2-byte units ? 65536 8 bits ? ram ? 4096 9 bits ? minimum bus cycle ? 62.5ns (cf=16mhz) note: the bus cycle time here refers to the rom read speed. ordering number : ena1220a cmos ic from 64k byte, ram 4k byte on-chip 8-bit 1-chip microcontroller with full-speed usb * this product is licensed from silicon storage technology, inc. (usa).
LC87F1D64A no.a1220-2/29 ? minimum instruction cycle time ? 188ns (cf=16mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1 bit units 28 (p10 to p17, p20 to p27, p30 to p34, p70 to p73, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 4 bit units 8 (p00 to p07) ? usb ports 2 (d+, d-) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for oscillation) 1 (xt1) ? reset pins 1 ( res ) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with t oggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? sio ? sio0: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 512/3 tcyc 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio4: synchronous serial interface 1) lsb first/msb first mode selectable 2) transfer clock cycle: 4/3 to 1020/3 tcyc 3) automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) 4) auto-start-on-falling-edge function 5) clock polarity selectable 6) crc16 calculator circuit built in LC87F1D64A no.a1220-3/29 ? full duplex uart ? uart1 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc ? uart2 1) data length: 7/8/9 bits selectable 2) stop bits: 1 bit (2 bits in continuous transmission mode) 3) baud rate: 16/3 to 8192/3 tcyc ? ad converter: 12 bits 12 channels ? 12/8 bits ad converter resolution selectable ? pwm: multifrequency 12-bit pwm 2 channels ? infrared remote control receiver circuit 1) noise reduction function (noise filter time constant: approx. 120 s, when the 32.768khz crystal oscilla tor is selected as the reference voltage source.) 2) supports data encoding systems such as ppm (pulse position modulation) and manchester encoding 3) x ? tal hold mode release function ? usb interface (function controller) ? compliant with usb 2.0 full-speed ? supports a maximum of 4 user-defined endpoints. endpoint ep0 ep1 ep2 ep3 ep4 transfer type control ? - - - - bulk - ? ? ? ? interrupt - ? ? ? ? isochronous - ? ? ? ? max. payload 64 64 64 64 64 ? watchdog timer ? external rc watchdog timer 1) interrupt and reset signals selectable ? internal counter watchdog timer 1) generates an internal reset signal on overflow occurring in a timer th at runs on a dedicated low-speed rc oscillator clock (30khz). 2) three operating modes are selectable: continues counting, stops counting, or retains count when the cpu ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) able to output oscillation clock of sub clock. LC87F1D64A no.a1220-4/29 ? interrupts ? 30 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/usb bus active /remote control receiver 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/usb bus reset/usb suspend/ uart1 receive/uart2 receive 8 0003bh h or l sio1/usb endpoint/usb-sof/sio4/uart1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/pwm0/pwm1 ? priority level: x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 2048 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock (1mhz) ? low-speed rc oscillation circuit (internal): for watchdog timer (30khz) ? cf oscillation circuit: for system clock ? crystal oscillation circuit: for system clock, time-of-day clock ? pll circuit (internal): for usb interface (see fig.5) ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) reset generated by watchdog timer (3) interrupt generation ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the pll base clock generator, cf, rc and cr ystal oscillators automatically stop operation. 2) there are five ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) reset generated by watchdog timer (3) having an interrupt source established at one of the int0, int1, int2, int4, and int5 pins * the int0 and int1 pins must be configured only for level detection. (4) having an interrupt source established at port 0 (5) having an bus active interrupt source established in the usb interface circuit continued on next page. LC87F1D64A no.a1220-5/29 continued from preceding page. ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circ uits except the base timer and the infrared remote control receiver circuit. 1) the pll base clock generator, cf and rc oscillator automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are seven ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) reset generated by watchdog timer (3) having an interrupt source established at one of the int0, int1, int2, int4, and int5 pins * the int0 and int1 pins must be configured only for level detection. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit (6) having an bus active interrupt source established in the usb interface circuit (7) having an interrupt source established in the infrared remote control receiver circuit ? package form ? sqfp48(7 7): lead-/halogen-free type ? development tools ? on-chip debugger: tcb87 type b + LC87F1D64A ? flash rom programming boards package programming boards sqfp48(7 7) w87f55256sq ? flash rom programmer maker model supported version device flash support group, inc. (fsg) single programmer af9708 af9709/af9709b/af9709c (including ando electric co., ltd. models) rev.03.06 or later LC87F1D64A flash support group, inc. (fsg) + our company (note 1) in-circuit programmer af9101/af9103 (main body) (fsg models) (note 2) sib87 (inter face driver) (our company model) our company single/gang programmer skk/skk type b (sanyo fws) application version 1.04 or later chip data version 2.15 or later lc87f1d64 in-circuit/gang programmer skk-dbg type b (sanyo fws) note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from our company (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or our comp any for the information. LC87F1D64A no.a1220-6/29 package dimensions unit : mm (typ) 3163b pin assignment sqfp48(7 7) ?lead-/ halogen-free type? p27/int5/dpup2 p26/int5/urx2 p25/int5/utx2 p24/int5/sck4 p23/int4/si4/wr p22/int4/so4/rd p21/int4/urx1 p20/int4/utx1 p07/an7/t7o p06/an6/t6o p05/an5/cko p04/an4 p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d- d+ v dd 3 v ss 3 p34/ufilt p33 p32/dbgp2 p31/dbgp1 p30/dbgp0 p70/int0/t0lcp/an8/dpup p71/int1/t0hcp/an9 p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 top view LC87F1D64A sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 LC87F1D64A no.a1220-7/29 sqfp48 name sqfp48 name 1 p73/int3/t0in/ rmin 25 p04/an4 2 res 26 p05/an5/cko 3 xt1/an10 27 p06/an6/t6o 4 xt2/an11 28 p07/an7/t7o 5 v ss 1 29 p20/int4/utx1 6 cf1 30 p21/int4/urx1 7 cf2 31 p22/int4/so4/ rd 8 v dd 1 32 p23/int4/si4/ wr 9 p10/so0 33 p24/int5/sck4 10 p11/si0/sb0 34 p25/int5/utx2 11 p12/sck0 35 p26/int5/urx2 12 p13/so1 36 p27/int5/dpup2 13 p14/si1/sb1 37 d- 14 p15/sck1 38 d+ 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1 41 p34/ufilt 18 pwm0 42 p33 19 v dd 2 43 p32/dbgp2 20 v ss 2 44 p31/dbgp1 21 p00/an0 45 p30/dbgp0 22 p01/an1 46 p70/int0/t0lcp/an8/dpup 23 p02/an2 47 p71/int1/t0hcp/an9 24 p03/an3 48 p72/int2/t0in LC87F1D64A no.a1220-8/29 system block diagram interrupt control from standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer base timer pwm1 int0 to 5 noise rejection filter sio0 port 2 usb pll port 7 port 3 sio1 timer 0 timer 1 pwm0 timer 6 timer 7 uart1 sio4 on-chip debugger usb interface adc infrared remote control receiver circuit uart2 LC87F1D64A no.a1220-9/29 pin description pin name i/o description option v ss 1, v ss 2, v ss 3 - -power supply pin no v dd 1, v dd 2 - +power supply pin no v dd 3 - usb reference voltage pin yes port 0 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input ? pins functions ad converter input port: an0 to an7 (p00 to p07) p05: system clock output p06: timer 6 toggle outputs p07: timer 7 toggle outputs yes p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output/beeper output yes p10 to p17 port 2 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20 to p23: int4 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p20: uart1 transmit p21: uart1 receive p22: sio4 date i/o/parallel interface rd output p23: sio4 date i/o/parallel interface wr output p24: sio4 clock i/o p25: uart2 transmit p26: uart2 receive p27: d+ 1.5k pull-up resistor connect pin interrupt acknowledge type yes p20 to p27 rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable continued on next page. LC87F1D64A no.a1220-10/29 continued from preceding page. pin name i/o description option port 3 i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p34: usb interface pll filter pin (see fig.5) on-chip debugger pins: dbgp0 to dbgp2 (p30 to p32) yes p30 to p34 port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/timer 0l capture input/watchdog timer output/ d+ 1.5k pull-up resistor connect pin p71: int1 input/hold reset input/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input/ infrared remote control receiver input ad converter input port: an8(p70), an9(p71) interrupt acknowledge type no p70 to p73 rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable pwm0 pwm1 i/o ? pwm0 and pwm1 output port ? general-purpose input port no d- i/o ? usb data i/o pin d- ? general-purpose i/o port no d+ i/o ? usb data i/o pin d+ ? general-purpose i/o port no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? pin functions general-purpose input port ad converter input port: an10 must be connected to v dd 1 if not to be used. no xt2 i/o 32.768khz crystal oscillator output pin ? pin functions general-purpose i/o port ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no LC87F1D64A no.a1220-11/29 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable (note 1) 2 nch-open drain no p10 to p17 p20 to p27 p30 to p34 1 bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no d+, d- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal oscillator output (n channel open drain when in general- purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4-bit units (p00 to 03, p04 to 07). user option table option name option to be applied on flash-rom version option selected in units of option selection port output type p00 to p07 ? 1 bit cmos nch-open drain p10 to p17 ? 1 bit cmos nch-open drain p20 to p27 ? 1 bit cmos nch-open drain p30 to p34 ? 1 bit cmos nch-open drain program start address - ? - 00000h 0fe00h usb regulator usb regulator ? - use nonuse usb regulator (at hold mode) ? - use nonuse usb regulator (at halt mode) ? - use nonuse LC87F1D64A no.a1220-12/29 power pin treatment connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. example 1: when the microcontroller is in the backup state in the hold mode, th e power to sustain the high level of output ports is supplied by their backup capacitors. example 2: the high level output at ports is not sustained and unstable in the hold backup mode. v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup lsi lsi v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply for backup LC87F1D64A no.a1220-13/29 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the active/inactive state of reference voltage circuit can be switched by the option select. the procedure for marking the option selection is described below. (1) (2) (3) (4) option select usb regulator use use use nonuse usb regulator at hold m ode use nonuse nonuse nonuse usb regulator at halt m ode use nonuse use nonuse reference voltage circuit state normal state active active active inactive hold mode active inactive inactive inactive halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increas e by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference voltage circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply 5v lsi d+ d- ufilt 0 2.2 5pf 1.5k p70/p27 2.2 f 0.1 f v ss 1 v ss 2v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v lsi d+ d- ufilt to usb connector 27 t o 33 5pf 0 2.2 p70/p27 2.2 f *1 *1: it is necessary to adjust the value with the ic mounted on the board. LC87F1D64A no.a1220-14/29 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 v input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1, xt2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ma ioph(2) pwm0, pwm1 per 1 applicable pin -20 ioph(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 average output current (note 1-1) iomh(1) ports 0, 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 iomh(3) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 total output current ioah(1) ports 0, 2 total of all applicable pins -25 ioah(2) port 1 pwm0, pwm1 total of all applicable pins -25 ioah(3) ports 0, 1, 2 pwm0, pwm1 total of all applicable pins -45 ioah(4) port 3 p71 to p73 total of all applicable pins -10 ioah(5) d+, d- total of all applicable pins -25 low level output current peak output current iopl(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 iopl(3) ports 3, 7, xt2 per 1 applicable pin 10 average output current (note 1-1) ioml(1) p02 to p07 ports 1, 2 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 ioml(3) ports 3, 7, xt2 per 1 applicable pin 7.5 total output current ioal(1) ports 0, 2 total of all applicable pins 45 ioal(2) port 1 pwm0, pwm1 total of all applicable pins 45 ioal(3) ports 0, 1, 2 pwm0, pwm1 total of all applicable pins 80 ioal(4) ports 3, 7, xt2 total of all applicable pins 15 ioal(5) d+, d- total of all applicable pins 25 allowable power dissipation pd max sqfp48(7 7) ta=-30 to +70 c 190 mw operating ambient temperature topr -30 +70 c storage ambient temperature tstg -55 +125 note 1-1: the mean output current is a mean value measured over 100ms. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty. LC87F1D64A no.a1220-15/29 allowable operating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.183 s tcyc 200 s 3.0 5.5 v 0.183 s tcyc 0.383 s usb circuit active 3.0 5.5 0.367 s tcyc 200 s except for onboard programming 2.7 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 high level input voltage v ih (1) ports 0, 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 2.7 to 5.5 0.9v dd v dd v ih (3) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) 2.7 to 4.0 v ss 0.2v dd v il (3) port 0 pwm0, pwm1 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) 2.7 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer side 2.7 to 5.5 v ss 0.8v dd -1.0 v il (6) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd instruction cycle time (note 2-2) tcyc 3.0 to 5.5 0.183 200 s usb circuit active 3.0 to 5.5 0.183 0.383 except for onboard programming 2.7 to 5.5 0.367 200 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 3.0 to 5.5 0.1 16 mhz ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.7 to 5.5 0.1 8 oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 16mhz ceramic oscillation see fig. 1. 3.0 to 5.5 16 mhz fmcf(2) cf1, cf2 8mhz ceramic oscillation see fig. 1. 2.7 to 5.5 8 fmrc internal rc oscillation 2.7 to 5.5 0.3 1.0 2.0 fmslrc internal low-speed rc oscillation 2.7 to 5.5 15 30 60 khz fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.7 to 5.5 32.768 note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. LC87F1D64A no.a1220-16/29 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 a i ih (2) xt1, xt2 for input port specification v in =v dd 2.7 to 5.5 1 i ih (3) cf1 v in =v dd 2.7 to 5.5 15 low level input current iil(1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 for input port specification v in =v ss 2.7 to 5.5 -1 i il (3) cf1 v in =v ss 2.7 to 5.5 -15 high level output voltage v oh (1) ports 0, 1, 2, 3 p71 to p73 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) pwm0, pwm1 p05 (ck0 when using system clock output function) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (6) i oh =-1ma 2.7 to 5.5 v dd -0.4 low level output voltage v ol (1) p00, p01 i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) i ol =1ma 2.7 to 5.5 0.4 v ol (7) ports 3, 7 i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) i ol =1ma 2.7 to 5.5 0.4 pull-up resistance rpu(1) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 4.5 to 5.5 15 35 80 k rpu(2) 2.7 to 5.5 18 50 150 hysteresis voltage vhys res ports 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf LC87F1D64A no.a1220-17/29 serial i/o characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) see fig.8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? see fig.8. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transmission/reception mode ? usb is in use simultaneous. ? sio4 is not in use simultaneous. ? see fig.8. ? (note 4-1-2) 7 tsckha(1c) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? see fig.8. ? (note 4-1-2) 9 output clock frequency tsck(2) sck0(p12) ? cmos output selected ? see fig.8. 2.7 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc tsckha(2b) ? continuous data transmission/ reception mode ? usb is in use simultaneous. ? sio4 is not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(2) +2tcyc tsckh(2) +(19/3) tcyc tsckha(2c) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? cmos output selected ? see fig.8. tsckh(2) +2tcyc tsckh(2) +(25/3) tcyc note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. continued on next page. LC87F1D64A no.a1220-18/29 continued from preceding page. parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial input data setup time tsdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 s data hold time thdi(1) 2.7 to 5.5 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11) ? continuous data transmission/reception mode ? (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.7 to 5.5 1tcyc +0.05 output clock tdd0(3) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig.8. 2. sio1 serial i/o characteristics (note 4-2-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) see fig.8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected ? see fig.8. 2.7 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 s data hold time thdi(2) 2.7 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.8. 2.7 to 5.5 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. add margin depending on its use. LC87F1D64A no.a1220-19/29 3. sio4 serial i/o characteristics (note 4-3-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(5) sck4(p24) see fig.8. 2.7 to 5.5 2 tcyc low level pulse width tsckl(5) 1 high level pulse width tsckh(5) 1 tsckha(5a) ? usb nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? see fig.8. ? (note 4-3-2) 4 tsckha(5b) ? usb is in use simultaneous. ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? see fig.8. ? (note 4-3-2) 7 tsckha(5c) ? usb and continuous data transmission/ reception mode of sio0 are in use simultaneous. ? see fig.8. ? (note 4-3-2) 10 output clock frequency tsck(6) sck4(p24) ? cmos output selected ? see fig.8. 2.7 to 5.5 4/3 low level pulse width tsckl(6) 1/2 tsck high level pulse width (note 4-3-3) tsckh(6) 1/2 tsckha(6a) ? usb nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(6) +(5/3) tcyc tsckh(6) +(10/3) tcyc tcyc tsckha(6b) ? usb is in use simultaneous. ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(6) +(5/3) tcyc tsckh(6) +(19/3) tcyc tsckha(6c) ? usb and continuous data transmission/reception mode of sio0 are in use simultaneous. ? cmos output selected ? see fig.8. tsckh(6) +(5/3) tcyc tsckh(6) +(28/3) tcyc serial input data setup time tsdi(3) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 s data hold time thdi(3) 2.7 to 5.5 0.03 serial output output delay time tdd0(5) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.8. 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input in continuous trans/rec mode, a time from si4run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-3-3: when using the serial clock output, make sure that the load at the sck4 (p 24) pin meets the following conditions: clock rise time tsckr < 0.037 s (see figure 11.) at ta=+25 c, v dd =3.3v LC87F1D64A no.a1220-20/29 pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tp1h(1) tp1l(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tpil(5) rmin(p73) recognized by the infrared remote control receiver circuit as a signal 2.7 to 5.5 4 rmck (note 5-1) tpil(6) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: represents the period of the reference clock (1 tcyc to 128 tcyc or the sour ce frequency of the subclock) for the infrared remote control receiver circuit. LC87F1D64A no.a1220-21/29 ad converter characteristics at ta= -30 c to +70 c, v ss 1 = v ss 2 = v ss 3 = 0v <12-bits ad converter mode> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 32 115 s 3.0 to 5.5 64 115 ad division ratio=1/16 3.0 to 5.5 50 115 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain=v dd 3.0 to 5.5 1 a iainl vain=v ss 3.0 to 5.5 -1 <8-bits ad converter mode> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p00) to an7(p07) an8(p70) an9(p71) an10(xt1) an11(xt2) 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb conversion time tcad see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 20 90 s 3.0 to 5.5 40 90 ad division ratio=1/16 3.0 to 5.5 31 90 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain=v dd 3.0 to 5.5 1 a iainl vain=v ss 3.0 to 5.5 -1 LC87F1D64A no.a1220-22/29 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop(1) v dd 1 =v dd 2 =v dd 3 ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 4.5 to 5.5 9.9 25 ma iddop(2) 3.0 to 3.6 5.7 14 iddop(3) ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 16mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 4.5 to 5.5 12 30 iddop(4) 3.0 to 3.6 6.8 17 iddop(5) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ration 4.5 to 5.5 14 35 iddop(6) 3.0 to 3.6 7.7 19 iddop(7) ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 16mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ration 4.5 to 5.5 16 40 iddop(8) 3.0 to 3.6 8.8 22 iddop(9) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 6.8 16 iddop(10) 3.0 to 3.6 4.1 9.7 iddop(11) 2.7 to 3.0 3.5 7.9 iddop(12) ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 8.2 20 iddop(13) 3.0 to 3.6 4.7 12 iddop(14) 2.7 to 3.0 4.0 9.2 iddop(15) ? fmcf=0mhz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? 1/2 frequency division ration 4.5 to 5.5 0.73 3.5 iddop(16) 3.0 to 3.6 0.43 1.9 iddop(17) 2.7 to 3.0 0.37 1.5 iddop(18) ? fmcf=0mhz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 45 174 a iddop(19) 3.0 to 3.6 18 86 iddop(20) 2.7 to 3.0 14 63 halt mode consumption current (note 7-1) iddhalt(1) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 4.5 to 5.5 4.9 12 ma iddhalt(2) 3.0 to 3.6 2.6 6.3 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page. LC87F1D64A no.a1220-23/29 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt(3) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 16mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ration 4.5 to 5.5 5.7 14 ma iddhalt(4) 3.0 to 3.6 3.1 7.6 iddhalt(5) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ration 4.5 to 5.5 8.9 23 iddhalt(6) 3.0 to 3.6 4.6 12 iddhalt(7) ? halt mode ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 16mhz side ? internal pll oscillation mode ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ration 4.5 to 5.5 9.7 24 iddhalt(8) 3.0 to 3.6 5.0 13 iddhalt(9) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 3.0 7.2 iddhalt(10) 3.0 to 3.6 1.6 3.8 iddhalt(11) 2.7 to 3.0 1.3 2.9 iddhalt(12) ? halt mode ? fmcf=16mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 3.5 8.6 iddhalt(13) 3.0 to 3.6 1.9 4.6 iddhalt(14) 2.7 to 3.0 1.5 3.5 iddhalt(15) ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? 1/2 frequency division ration 4.5 to 5.5 0.41 2.0 iddhalt(16) 3.0 to 3.6 0.20 0.93 iddhalt(17) 2.7 to 3.0 0.16 0.69 iddhalt(18) ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped ? 1/2 frequency division ration 4.5 to 5.5 32 134 a iddhalt(19) 3.0 to 3.6 8.8 60 iddhalt(20) 2.7 to 3.0 6.0 40 hold mode consumption current iddhold(1) v dd 1 hold mode ? cf1=v dd or open (external clock mode) 4.5 to 5.5 0.08 30 iddhold(2) 3.0 to 3.6 0.03 18 iddhold(3) 2.7 to 3.0 0.02 15 iddhold(4) hold mode ? internal counter watchdog timer operation mode (internal low-speed rc oscillation circuit operation) ? cf1=v dd or open (external clock mode) 4.5 to 5.5 2.9 38 iddhold(5) 3.0 to 3.6 1.4 23 iddhold(6) 2.7 to 3.0 1.2 20 timer hold mode consumption current iddhold(7) v dd 1 timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 4.5 to 5.5 27 118 iddhold(8) 3.0 to 3.6 6.1 51 iddhold(9) 2.7 to 3.0 3.8 34 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. LC87F1D64A no.a1220-24/29 usb characteristics and timing at ta = 0c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol conditions specification min typ max unit high level output v oh(usb) ? 15k 5% to gnd 2.8 3.6 v low level output v ol(usb) ? 1.5k 5% to 3.6 v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? |(d+)-(d-)| 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 v low level input v il(usb) 0.8 v usb data rise time t r ? r s =27 to 33 , cl=50pf ? v dd 3=3.0 to 3.6v 4 20 ns usb data fall time t f ? r s =27 to 33 , cl=50pf ? v dd 3=3.0 to 3.6v 4 20 ns f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2= v ss 3 =0v parameter symbol pin conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma programming time tfw(1) ? erase operation 3.0 to 5.5 20 30 ms tfw(2) ? write operation 40 60 s LC87F1D64A no.a1220-25/29 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system cl ock oscillator circuit with a ceramic oscillator at ta = 0c to +70c nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rd1 [ ] typ [ms] max [ms] 8mhz murata cstce8m00g15l**-r0 ( 33) (33) 680 2.7 to 5.5 0.1 0.5 c1 and c2 integrated smd type 12mhz murata cstce12m0g15l**-r0 ( 33) (33) 470 3.0 to 5.5 0.1 0.5 16mhz murata cstce16m0v13l**-r0 (15) (15) 330 3.0 to 5.5 0.05 0.25 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after v dd goes above the operating voltage lower limit. ? till the oscillation gets stabilized after the instruction fo r starting the main clock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset. ? till the oscillation gets stabilized after the x'tal hold mode is reset with cfstop (ocr register, bit 0) set to 0 characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf [ ] rd2 [ ] typ [s] max [s] 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to 5.0 1.1 3.0 applicable cl value=12.5pf smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is reset with extosc (ocr register, bit 6) set to 1 note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit c1 c2 cf cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf rd1 LC87F1D64A no.a1220-26/29 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time 0.5v dd operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd gnd execute oscillation enable instruction. internal rc oscillation cf1, cf2 xt1, xt2 operating mode hold release signal hold release signal valid tmscf tmsx?tal hold halt * when oscillation is enabled before entry into hold mode LC87F1D64A no.a1220-27/29 figure 5 external filter circuit for th e internal usb-dedicated pll circuit figure 6 usb port peripheral circuit figure 7 reset circuit c res v dd r res res rd 0 cd 2.2 f p34/ufilt + - when using the internal pll circuit to generate the 48mhz clock for usb , it is necessary to connect a filter circuit such as that shown to the left to the p34/ufilt pin. 5pf 27 to 33 d- d+ 5pf 27 to 33 1.5k p70/ p27 vd3oen/ vd3oen2 note: it?s necessary to adjust the circuit constant of the usb port peripheral circuit each mounting board. make the d+ pull-up resistors available to control on/off according to the vbus. note: determine the value of c res and r res so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the ic's operating voltage. LC87F1D64A no.a1220-28/29 figure 8 serial i/o waveforms figure 9 pulse input timing signal waveform figure 10 usb data signal timing and voltage level tpil tpih data ram transfer period (sio0, 4 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0, 4 only) t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol LC87F1D64A no.a1220-29/29 figure 11 serial clock output timing signal waveform ps v ih (1) min=0.3v dd +0.7v tsckr tsckr: defined as the time period from the time the state of the output starts changing till the time it reaches the value of v ih (1). on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. |
Price & Availability of LC87F1D64A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |